Cypress Semiconductor STK14C88-3 Manual de usuario descargar pdf (Pagina 5)

AN55662

October 5, 2009 Document No. 001-55662 Rev. ** 5

Details of Improvement

Hardware STORE Related Improvements

HSB

pin (Hardware STORE Busy Indication/Hardware

STORE Initiation)

The

HSB

pin of the nvSRAM is an open drain I/O pin used

to indicate or initiate a STORE operation. When a STORE

operation is in progress, nvSRAM pulls the

HSB

pin low to

indicate that the device is busy and cannot be accessed for

read/write operation. During normal operation, the

HSB

can be pulled low to initiate a Hardware STORE operation.

As shown in Table 5, several timing parameters related to

the

HSB

pin input and output have changed from

STK14C88-3 to CY14B256LA. All of these changes are

improvements from the original part specification and should

be considered as added benefits in your system while

converting to the new part number.

Write Latch: When a write operation is done, a ‘write latch’ is

set internally. When

HSB

is pulled low, nvSRAM checks

this write latch before initiating a STORE. This is done to

prevent any unnecessary loss of endurance cycles.

DELAY

If a write latch is set and the

HSB

pin is pulled low,

STK14C88-3 enables 1 us time for write operations to

complete before STORE operation begins and reads and

writes are inhibited. This potentially enables inadvertent data

to be written to the nvSRAM during the t

DELAY

duration.

In CY14B256LA, the t

DELAY

parameter enables only one

write cycle time for any ongoing write to complete after

HSB

pin is pulled low. This improvement provides better security

from inadvertent write operations.

Also, if

HSB

pin is pulled low externally for a minimum of

PHSB

time on CY14B256LA, the output driver of

HSB

pulls the pin low only indicating a STORE operation within

25 ns (t

DELAY

). This parameter for

HSB

low to STORE busy

is not specified in the STK14C88-3. (See Figure 1 and

Figure 2)

HSB

LOW when write latch not set:

If no writes are performed since the last STORE/RECALL

operation, STORE operation does not start when

HSB

pulled low. However, the

HSB

pin is still internally pulled

low for 1 us (t

DELAY

) time in the STK14C88-3 device.

CY14B256LA device does not pull the

HSB

pin low

internally if write latch is not set.

Figure 1. STK14C88-3: AC Parameters Related to

HSB

Figure 2. CY14B256LA: AC Parameters Related to

HSB

Write Latch Set Write Latch Not Set

[+] Feedback

1 2 3 4 5 6 7 8

Comentarios a estos manuales

Sin comentarios

Cypress Semiconductor STK14C88-3 Manual de usuario Pagina 5

Comentarios a estos manuales

Relacionado con productos y manuales para No Cypress Semiconductor STK14C88-3