Cypress Semiconductor STK12C68-5 Manual de usuario descargar pdf (Pagina 2)

STK12C68-5 (SMD5962-94599)

Document Number: 001-51026 Rev. ** Page 2 of 18

Pinouts

Pin Definitions

Pin Name Alt IO Type Description

–A

Input Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.

-DQ

Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.

Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO

pins is written to the specific address location.

Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the

chip.

Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during

read cycles. Deasserting OE

HIGH causes the IO pins to tri-state.

Ground Ground for the Device. The device is connected to ground of the system.

Power Supply Power Supply Inputs to the Device.

HSB

Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in

progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A

weak internal pull up resistor keeps this pin high if not connected (connection optional).

CAP

Power Supply AutoStore

Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM

to nonvolatile elements.

Figure 1. Pin Diagram - 28-Pin DIP

Figure 2. Pin Diagram - 28-Pin LLC

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Cypress Semiconductor STK12C68-5 Manual de usuario Pagina 2