Cypress Semiconductor Perform STK12C68 Manual de usuario descargar pdf (Pagina 10)

STK12C68

Document Number: 001-51027 Rev. *G Page 10 of 22

AC Switching Characteristics

SRAM Read Cycle

Parameter

Description

25 ns 35 ns 45 ns

Unit

Min Max Min Max Min Max

Cypress

Parameter

Alt

ACE

ELQV

Chip enable access time – 25 – 35 – 45 ns

[7]

AVAV,

ELEH

Read cycle time 25 – 35 – 45 – ns

[8]

AVQV

Address access time – 25 – 35 – 45 ns

DOE

GLQV

Output enable to data valid – 10 – 15 – 20 ns

OHA

[8]

AXQX

Output hold after address change 5 – 5 – 5 – ns

LZCE

[9]

ELQX

Chip enable to output active 5 – 5 – 5 – ns

HZCE

[9]

EHQZ

Chip disable to output inactive – 10 – 10 – 12 ns

LZOE

[9]

GLQX

Output enable to output active 0 – 0 – 0 – ns

HZOE

[9]

GHQZ

Output disable to output inactive – 10 – 10 – 12 ns

[6]

ELICCH

Chip enable to power active 0 – 0 – 0 – ns

[6]

EHICCL

Chip disable to power standby – 25 – 35 – 45 ns

Switching Waveforms

Figure 7. SRAM Read Cycle 1: Address Controlled

[7, 8]

Figure 8. SRAM Read Cycle 2: CE and OE Controlled

[7]

OHA

ADDRESS

DQ (DATA OUT)

DATA VALID

ADDRESS

ACE

LZCE

HZCE

DOE

LZOE

HZOE

DATA VALID

ACTIVE

STANDBY

DQ (DATA OUT)

ICC

Notes

7. WE

and HSB must be High during SRAM Read cycles.

8. Device is continuously selected with CE

and OE both Low.

9. Measured ±200 mV from steady state output voltage.

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 21 22

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