Cypress Semiconductor NoBL CY7C1462AV25 Manual de usuario descargar pdf (Pagina 11)

CY7C1460AV25

CY7C1462AV25

Document Number: 38-05354 Rev. *J Page 11 of 31

Partial Write Cycle Description

The partial write cycle description table for CY7C1462AV25 follows.

[12, 13, 14, 15]

Function (CY7C1462AV25) WE BW

Read H X X

Write – no bytes written L H H

Write byte a – (DQ

and

DQP

)LHL

Write byte b – (DQ

and

DQP

)LLH

Write both bytes L L L

Notes

12. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE

stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies

that the desired byte write selects are asserted, see Write Cycle Description table for details.

13. Write is defined by WE

and BW

. See Write Cycle Description table for details.

14. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

15. Table only lists a partial listing of the byte write combinations. Any combination of BW

is valid. Appropriate write will be done based on which byte write is active.

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Cypress Semiconductor NoBL CY7C1462AV25 Manual de usuario Pagina 11