
Document Number: 38-02009 Rev. *K Page 2 of 17
16
TXD[15:0]
Input
Register
Shifter
TXCLKI
LOCKREF
TX PLL
X16
FIFO
IN
±
OUT
±
÷
16
(155.52 MHz)
LOOPTIME
TX Bit-Clock
REFCLK
±
DIAGLOOP
LINELOOP
LOOPA
16
Output
Register
RXD[15:0]
Shifter
RX CDR
PLL
÷
16
RXCLK
(155.52 MHz)
Recovered
Bit-Clock
Retimed
Data
(155.52 MHz)
Lock-to-Data/
Clock Control
Logic
Lock-to-Ref
LFI
SD
FIFO_ERR TXCLKO
FIFO_RST
RESETPWRDN
Logic Block Diagram
Comentarios a estos manuales