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Cypress Semiconductor CY7C1019CV33 Manual de usuario

Busca en linea o descarga Manual de usuario para No Cypress Semiconductor CY7C1019CV33. CY7C1018DV33/CY7C1019DV33, 1-Mbit (128 K × 8 Manual de usuario

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CY7C1018DV33
CY7C1019DV33
1-Mbit (128 K × 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05481 Rev. *I Revised November 19, 2014
1-Mbit (128 K × 8) Static RAM
Features
■ Pin- and function-compatible with CY7C1018CV33 and
CY7C1019CV33
■ High speed
❐ t
AA
= 10 ns
■ Low Active Power
❐ I
CC
= 60 mA @ 10 ns
■ Low CMOS Standby Power
❐ I
SB2
= 3 mA
■ 2.0 V Data retention
■ Automatic power-down when deselected
■ CMOS for optimum speed/power
■ Center power/ground pinout
■ Easy memory expansion with CE
and OE options
■ Available in Pb-free 32-pin 400-Mil wide Molded SOJ, 32-pin
TSOP II and 48-ball VFBGA packages
Functional Description
The CY7C1018DV33/CY7C1019DV33 is a high-performance
CMOS static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE
), an active LOW Output Enable (OE), and three-state
drivers. This device has an automatic power-down feature that
significantly reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE
) inputs LOW. Data on the eight I/O pins
(I/O
0
through I/O
7
) is then written into the location specified on
the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip Enable
(CE
) and Output Enable (OE) LOW while forcing Write Enable
(WE
) HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH),
the outputs are disabled (OE
HIGH), or during a write operation
(CE
LOW, and WE LOW).
The CY7C1018DV33/CY7C1019DV33 are available in Pb-free
32-pin 400-Mil wide Molded SOJ, 32-pin TSOP II and 48-ball
VFBGA packages.
For a complete list of related documentation, click here.
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUTBUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
13
A
11
A
12
A
9
A
10
128K × 8
ARRAY
A
14
A
15
A
16
Logic Block Diagram
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Indice de contenidos

Pagina 1 - 1-Mbit (128 K × 8) Static RAM

CY7C1018DV33CY7C1019DV331-Mbit (128 K × 8) Static RAMCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Do

Pagina 2

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 10 of 19Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [20, 21]Switching Wavefor

Pagina 3

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 11 of 19Truth TableCE OE WE I/O0–I/O7Mode PowerH X X High Z Power-Down Standby (ISB)L

Pagina 4

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 12 of 19Ordering Code DefinitionsOrdering InformationSpeed (ns)Ordering CodePackage Di

Pagina 5

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 13 of 19Package DiagramsFigure 10. 32-pin SOJ (400 Mils) V32.4 (Molded SOJ V33) Packa

Pagina 6

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 14 of 19Figure 11. 32-pin SOJ (300 Mils) V32.3 (Catalog 32.3 Molded SOJ) Package Outl

Pagina 7

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 15 of 19Figure 12. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32 Package Outline, 51-8

Pagina 8

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 16 of 19Figure 13. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150

Pagina 9

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 17 of 19Acronyms Document ConventionsUnits of MeasureAcronym DescriptionCEChip EnableC

Pagina 10 - CY7C1019DV33

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 18 of 19Document History PageDocument Title: CY7C1018DV33/CY7C1019DV33, 1-Mbit (128 K

Pagina 11

Document Number: 38-05481 Rev. *I Revised November 19, 2014 Page 19 of 19All products and company names mentioned in this document may be the tradema

Pagina 12

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 2 of 19ContentsSelection Guide ...

Pagina 13

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 3 of 19Selection GuideDescription -10 (Industrial) UnitMaximum Access Time 10 nsMaximu

Pagina 14

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 4 of 19Maximum RatingsExceeding maximum ratings may impair the useful life of thedevic

Pagina 15

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 5 of 19CapacitanceParameter [3]Description Test Conditions Max UnitCINInput Capacitanc

Pagina 16

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 6 of 19Data Retention CharacteristicsOver the Operating RangeParameter Description Con

Pagina 17

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 7 of 19Switching CharacteristicsOver the Operating RangeParameter [7]Description-10 (I

Pagina 18 - Characteristics table

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 8 of 19Switching WaveformsFigure 5. Read Cycle No. 1 (Address Transition Controlled)

Pagina 19

CY7C1018DV33CY7C1019DV33Document Number: 38-05481 Rev. *I Page 9 of 19Figure 7. Write Cycle No. 1 (CE Controlled) [17, 18]Figure 8. Write Cycle No.

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