PRELIMINARY
CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *B Page 8 of 28
ignored during this cycle. If a global write is conducted, the
data presented to the DQ
[x:0]
is written into the corresponding
address location in the RAM core. If a byte write is conducted,
only the selected bytes are written. Bytes not selected during
a byte write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Because the CY7C1380C/CY7C1382C is a common I/O
device, the Output Enable (OE
) must be deasserted HIGH
before presenting data to the DQ
[x:0]
inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ
[x:0]
are automatically three-stated whenever a write cycle is
detected, regardless of the state of OE
.
Burst Sequences
The CY7C1380C/CY7C1382C provides a two-bit wraparound
counter, fed by A
[1:0]
, that implements either an interleaved or
linear burst sequence. The interleaved burst sequence is
designed specifically to support Intel Pentium applications.
The linear burst sequence is designed to support processors
that follow a linear burst sequence. The burst sequence is user
selectable through the MODE input.
Asserting ADV
LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
s, ADSP, and ADSC must remain
inactive for the duration of t
ZZREC
after the ZZ input returns
LOW.
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A
[1:0]
A
[1:0]
A
[1:0]
A
[1:0]
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A
[1:0]
A
[1:0]
A
[1:0]
A
[1:0]
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
I
DDZZ
Sleep mode standby current ZZ > V
DD
– 0.2V 60 mA
t
ZZS
Device operation to ZZ ZZ > V
DD
– 0.2V 2t
CYC
ns
t
ZZREC
ZZ recovery time ZZ < 0.2V 2t
CYC
ns
Cycle Descriptions
[1, 2, 3, 4]
Next Cycle Add. Used ZZ CE
3
CE
2
CE
1
ADSP ADSC ADV OE DQ Write
Unselected None 0 X X 1 X 0 X X Hi-Z X
Unselected None 0 1 X 0 0 X X X Hi-Z X
Unselected None 0 X 0 0 0 X X X Hi-Z X
Unselected None 0 1 X 0 1 0 X X Hi-Z X
Unselected None 0 X 0 0 1 0 X X Hi-Z X
Begin Read External 0 0 1 0 0 X X X Hi-Z X
Begin Read External 0 0 1 0 1 0 X X Hi-Z Read
Continue Read Next 0 X X X 1 1 0 1 Hi-Z Read
Continue Read Next 0 X X X 1 1 0 0 DQ Read
Continue Read Next 0 X X 1 X 1 0 1 Hi-Z Read
Notes:
1. X = “Don't Care.” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE
, BWx, and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE
signal. OE is asynchronous and is not sampled with the clock.
4. CE
1
, CE
2
, and CE
3
are available only in the TQFP package. The BGA package has a single chip select, CE
1
.
(19 paginas)
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