Cypress Semiconductor MoBL-USB CY7C68000A Especificaciones descargar pdf (Pagina 11)

CY7C68000A

Document #: 38-08052 Rev. *H Page 11 of 15

HS/FS Interface Timing - 30 MHz

Figure 4. 30 MHz Timing Interface Timing Constraints

Figure 5. Tristate Mode Timing Constraints

Table 5. Tristate Mode Timing Constraints Parameters

Table 4. 30 MHz Timing Interface Timing Constraints Parameters

Parameter Description Min Typ Max Unit Notes

CSU_MIN

Minimum setup time for TXValid 16 ns

CH_MIN

Minimum hold time for TXValid 1 ns

DSU_MIN

Minimum setup time for Data (Transmit direction) 16 ns

DH_MIN

Minimum hold time for Data (Transmit direction) 1 ns

CCO

Clock to Control Out time for TXReady, RXValid,

RXActive and RXError

120ns

CDO

Clock to Data out time (Receive direction) 1 20 ns

VSU_MIN

Minimum setup time for ValidH (transmit Direction) 16 ns

VH_MIN

Minimum hold time for ValidH (Transmit direction) 1 ns

CVO

Clock to ValidH out time (Receive direction) 1 20 ns

Parameter Description Min Typ Max Unit Notes

tssu

Minimum setup time for Tristate 0 ns

tspd

Propagation Delay for Tristate mode 50 ns

TCSU_MIN

TCH_MIN

TDSU_MIN

TDH_MIN

TCVO

TCCO

DataIn

DataOut

Control_Out

Control_In

CLK

TCDO

TVSU_MIN

TVH_MIN

Ttssu Ttspd

Ttspd

Suspend

Tri-state

Output / IO XXXX Hi-Z

[+] Feedback

1 2 ... 6 7 8 9 10 11 12 13 14 15

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