Cypress Semiconductor Perform CY7C1380D Especificaciones descargar pdf (Pagina 22)

3–10 Chapter 3: Building the SOPC System

Coordinate Components in the System

Nios II System Architect Design Tutorial © June 2009 Altera Corporation

Preliminary

9. If the clock ports for the components do not appear in the Module Name column,

perform the following steps:

a. Click the Filters button below your system display.

b. In the Filters dialog box, under Filter, select All.

c. Close the Filters dialog box.

10. To change the clocks for the individual components, for each component, click the

Clock column and select the desired clock name according to Table 3–3.

Table 3–3 lists the clocks for the different component ports. For each clock,

components are listed in the order they appear in the SOPC Builder System

Contents tab.

Figure 3–8. Clocks for Digital Picture Viewer SOPC Builder System

Table 3–3. Clocks for Individual Components in Digital Picture Viewer SOPC Builder System

Clock Name Frequency Source Component Port

osc_clk 50 MHz Oscillator ddr_sdram/refclk

ddr_sdram_sysclk 75 MHz SDRAM PLL lcd_ta_sgdma_to_fifo/clk

lcd_pixel_fifo/clk_in

ddr_sdram/s1

cpu_ddr_clock_bridge/clk_m1

lcd_sgdma/clk

cpu_clk 100 MHz External PLL sysid/clk

flash_ssram_tristate_bridge/clk

ssram/clk

ext_flash/clk

jtag_uart/clk

sys_clk_timer/clk

lcd_i2c_scl/clk

lcd_i2c_en/clk

lcd_i2c_sdat/clk

pio_id_eeprom_scl/clk

pio_id_eeprom_dat/clk

touch_panel_spi/clk

touch_panel_pen_irq_n/clk

lcd_pixel_fifo/clk_out

lcd_ta_fifo_to_dfa/clk

lcd_64_to_32_bits_dfa/clk

lcd_pixel_converter/clk

lcd_24_to_8_bits_dfa/clk

lcd_sync_generator/clk

cpu/clk

cpu_ddr_clock_bridge/clk_s1

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 45 46

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